1. Field of the Invention
The present invention relates generally to computer systems, and more particularly to memory controlling devices. Specifically, the present invention is directed toward a programmable memory controller that provides faster memory access rates by using pairs of memory segments and optimally controlling the timing sequences between the pairs of segments by optimally ordering a plurality of pending memory requests between a plurality of requestors.
2. Related Art
The two most common types of semiconductor random access memories (RAMs) used in modern computer systems are static random access memory (SRAM), and dynamic random access memory (DRAM). Typically DRAMs are most often used when large amounts of memory are required, such as for an implementation of a computer system's primary storage. SRAMs are used most often when smaller amounts of memory are required and/or faster access rates are desired. For example, SRAMs are often used in computer systems as fast cache memory.
DRAMs are most often implemented when large amounts of memory are needed due to their lower costs and space requirements compared to SRAMs. However, the use of DRAMs require more complicated support circuitry than SRAMs. SRAMs store bits of data in an array of flip-flops. Once a bit is written in a SRAM, it remains there until it is either changed by another write sequence or energy is removed from the memory circuit.
DRAMs, on the other hand, store bits of data as charged capacitors. Because DRAMs are typically implemented using only a single transistor per bit of storage, they can be fabricated much more densely than SRAMs which typically require from 4-6 transistors per bit. However, because DRAMs store bits of data as charges, they are unstable because the charges leak off in a very short amount of time, usually within a few milliseconds. Thus, if DRAMs are not continuously attended to by a procedure known as `refresh` they are subject to memory loss.
Refresh is accomplished by accessing the data within each cell in a DRAM. DRAM chips are generally organized in a matrix having rows and columns. In order to effectively perform refresh operations without taking an inordinate amount of time by continuously reading and writing to each cell every couple of milliseconds, DRAMs are organized so that an entire row may be refreshed during a single operation. This feature dramatically decreases the amount of time spent on refresh cycles.
Additionally, the row/column organization of DRAMs facilitates the use of fewer address lines that need to be connected to each DRAM chip. Each memory location within a DRAM is addressed by specifying a particular row address and a particular column address. The intersection of a row and column address identifies a specific memory location. By time multiplexing the row address and the column addresses, the same address lines can be used for both components of the address, thereby reducing the number of required address lines.
For example a DRAM chip that has a capacity of 64 Mbits may be arranged as a matrix comprising 8192 columns and 8192 rows. Generally, in order to address 64 Mbits of data using linear addressing techniques, 26 address lines are required. However, by time multiplexing the row and column address (i.e. by presenting the row address, followed by the column address), only 13 address lines are required.
In order to handle the refresh, address multiplexing, and other stringent control and timing requirements of DRAMS (discussed below), complex support circuitry is required. This is to be contrasted with the relatively simple support circuitry required by SRAMs. However, such complex support circuitry can be shared among large arrays of DRAMs making the additional cost less significant for systems that employ large memory arrays. Indeed, for systems that employ large memory arrays, the savings realized in both semiconductor real estate and lower memory costs generally outweigh the additional expense associated with the complex support circuitry.
Thus, computer system design engineers who wish to use DRAMs in their system designs must supply the required DRAM support circuitry. Generally, DRAM manufacturers provide specifications for each type of DRAM they produce. Such specifications comprise information needed to support each operating mode of the DRAM. Frequently, the specifications include timing diagrams comprising a plurality of digital waveforms. Each timing diagram depicts the control signals and their associated timings that are required to support each mode of operation of the DRAM. Typically, DRAMs support at least three modes of operation: a read, a write, and a refresh. A typical read cycle sequence can involve more than 20 timing parameters, all of which must be held within the specified limits to insure proper read operations. Write and refresh cycle timings are similarly complex.
The timing requirements, refresh requirements and the address multiplexing techniques used for DRAMs all tend to increase the access time. Typically, access times for the fastest commercial off the shelf (COTS) DRAMs commonly available today are in the range of 50-70 nano seconds (ns). This is to be contrasted with access times for the fastest COTS SRAMs, which are in range of 5-15 ns. The control timing requirements of DRAMs are partially responsible for their relatively long access times.
Such control timings are often the cause of undesirable wait cycles during and between memory access operations. Typically, a fixed period of time must elapse before and after a DRAM memory access operation. For example, pursuant to a DRAM read operation, several sequential events must occur before data is output on the data bus. This time period is referred to herein as the set-up time. Likewise, after a DRAM memory read operation has taken place, a fixed period of time must elapse before the DRAM is ready to accept another memory access command. This time period is referred to herein as the row address strobe (RAS) precharge time. Thus, using conventional methods, system data busses are not utilized to their optimal capacity when using DRAM devices. It is common for such data busses to sit idle for significant periods of time during and between memory access sequences.